1. Field of the Invention
The present invention relates to a memory device including one transistor type memory cells. More particularly, it relates to a memory device, in which a speed for write operation of H level voltage from bit lines to the memory cells can be made to faster, and to a method for driving the memory device.
2. Description of the Related Art
Capacity of a Dynamic RAM (DRAM) having one transistor type memory cells has been increased, and the power supply voltage has been lowered. It has been proposed that a power supply voltage, which is now3.3 V, is made to 2.5V or 1.8V, for example. Therefore, a DRAM should be developed for reading or writing data in high speed even when it is under the lower power supply voltage.
FIG. 1 is a circuit diagram of the conventional DRAM. As is shown in FIG. 1, the conventional DRAM includes memory cells MC.sub.0 and MC.sub.1 disposed at the cross-positions between a bit line pair BL and /BL and a word line pair WL.sub.0 and WL.sub.1. The memory cells MC.sub.0 and MC.sub.1 respectively include transistors Q.sub.0 and Q.sub.1 and capacitors ST. A sense amplifier SA, an equalizing circuit 200 for shorting between the bit lines, and a pre-charging circuit 100 for driving the bit line pairs to a pre-charge voltage are provided to the bit line pair BL and /BL.
FIG. 2 is an operating waveform diagram for the read operation in the conventional DRAM of FIG. 1. The read operation will be now explained in accompanying to FIG. 2 in brief. At first, pre-charging and equalizing are released in status where the bit line pair BL and /BL are pre-charged to a level V.sub.ii /2, which is half of the internal power supply V.sub.ii. Then, the bit line pair BL and /BL are temporally in floating status. When the word line WL.sub.0 rises, charges of the capacitor ST in the memory cell MC.sub.0 storing H level are supplied to the bit line BL to increase the voltage of the bit line BL for very small voltage. The sense amplifier SA detects a voltage difference between the bit line pair by driving each of sense amplifier activation signals SE and /SE, and drives one bit line BL to the internal power supply V.sub.ii and the other bit line /BL to the ground voltage GND. The levels of the bit lines are externally read out via data bus lines, not shown in the diagram.
When driving the bit line BL to the internal power supply V.sub.ii, the above-described amplifier SA also drives the capacitor voltage ST in the memory cell MC.sub.0 to the internal power supply V.sub.ii via a cell transistor Q.sub.0, in the same way of that. Then the word line WL.sub.0 falls so that the capacitor voltage ST in the memory cell MC.sub.0 maintains the internal power supply level V.sub.ii. Then, the bit line pair BL and /BL are reset to the pre-charge voltage level V.sub.ii /2, again, by rising a bit line reset signal BLR.
FIG. 3 shows an operating waveform diagram for write operation in the conventional DRAM of FIG. 1. The writing operation is different from the read operation shown in FIG. 2. After the sense amplifier SA drives the bit line pair BL and /BL, a writing circuit, not shown in the diagram, drives the bit line pair BL and /BL. In the example of FIG. 3, the read operation of data at L level for the memory cell MC.sub.0, and the write operation of data at H level after the read operation are shown. In this case, the condition of the sense amplifier SA is reversed, the bit line BL is driven from the ground voltage to the power supply voltage V.sub.ii, and the voltage V.sub.ii is stored in the capacitor ST of the memory cell MC.sub.0.
In the conventional DRAM, as shown in FIG. 2, the pre-charge voltage of the bit lines is set to a voltage V.sub.ii /2, which is half of the internal power supply V.sub.ii, and the drive voltage of the H level bit line and a capacitor voltage for H level in the memory cell according to the drive voltage are set to the internal power supply V.sub.ii. The pair of bit lines are driven to the voltage V.sub.ii for the H level and to the ground voltage for the L level, so as to charge the capacitors in the memory cells with each voltage. Then, the bit line pair is reset to the pre-charge voltage V.sub.ii /2 again by shorting the bit line pair.
However, when the above-described conventional memory device writes or re-writes data to memory cells, since the voltage V.sub.BLD (=V.sub.ii) of the H level bit line and the H level voltage V.sub.ST (=V.sub.ii) of the capacitor ST in the memory cell are set to the same voltage level V.sub.ii, therefore, it takes a long time to pull up the voltage V.sub.ST of the cell capacitor ST to the voltage V.sub.ii for the H level. In other words, the word line WL is driven to a voltage higher than the voltage V.sub.ii on the H level bit line for a threshold voltage V.sub.th1 of the cell transistor or more. Therefore, a sufficient high voltage is applied to a gate of the cell transistor. However, when considering a relationship between the voltage V.sub.ii of the bit line and the voltage V.sub.ST of the cell capacitor ST, as the voltage V.sub.ST of the cell capacitor ST is being close to the voltage V.sub.ii of the bit line, a voltage V.sub.ds between a source and a drain of the cell transistor becomes small, and an amount of currents flowing from the bit line to the cell capacitor ST becomes smaller. As a result, it takes a long time for the voltage V.sub.ST of the cell capacitor ST to reach to the voltage V.sub.ii of the bit line.
Although there is a general demand to make the speed of the read operation to faster, it is also required to shorten a cycle time for random access by shortening write or re-write operation to the memory cell. Therefore, it is important to reduce the operation time of writing and re-writing to the memory cell.
In this case, it is considered as one solution that the cell capacitor voltage is only set to be lower than the drive voltage on the H level bit line in order to prevent a slow operation in an area where the voltage V.sub.ds of the cell transistor is lowered. However, if the voltage is set in such a way in case the pre-charge voltage of the bit lines is set to a voltage V.sub.ii /2, which is half of the voltage of the H level bit line, the increased voltage of the bit line when driving the word line becomes smaller in accordance to the lowered H level voltage in the memory cell, thus making it difficult to detect a very small voltage difference between the bit line pair by the sense amplifier.